The interconnection layers of an integrated circuit permit electrical connections to be made to various underlying silicon devices, such as transistors or other components. In order to provide a solution that is relatively economic in terms of surface area and cost, an interconnection layer is generally based on a series of parallel interconnection lines formed across the integrated circuit. These parallel lines are modified to suit a given application by features such as connections between the lines and cuts in the lines.
For interconnection technologies where a pitch between the lines of 90 nm or less is to be achieved, it has been proposed to use unidirectional masks, meaning that each mask comprises lines or line portions running in one direction only. This means that there is an added constraint that it is no longer possible to form, at the same time as the parallel interconnection lines, connections running perpendicular to these lines. This constraint adds complexity and cost to the process of forming interconnections.
Therefore, there is a general need for an improved method of forming, on an integrated circuit, interconnection lines having a low pitch.